As CMOS technology scales down, the size of the detector itself becomes an impediment to the further scaling of CMOS single photon avalanche diode (SPAD) arrays. In order to further scale the SPAD detector, the guard ring size of p-well/DNW (deep n-well) SPAD was designed, and SPADs with varied guard ring sizes were fabricated in a 0.18 μm CMOS Image Sensor (CIS) technology. The measured results show that, the guard ring with its size decreased to 0.4 μm is effective in preventing premature edge breakdown (PEB), and SPADs with guard ring size more than 0.4 μm exhibit good avalanche breakdown characteristics with a breakdown voltage of 16 V. Moreover, the guard ring size does not have a significant impact on the dark count rate (DCR) and the photon detection probability (PDP) of p-well/DNW SPADs, and the SPADs for 20 μm diameter active area structure achieve a low DCR of 638 Hz at 25 ℃ and a broader spectral response with a PDP peak of 16% at 530 nm.